Vias are routinely used structures in the construction of integrated circuit (IC) devices. By way of example, vias may be used to form electrical connections between various layers of conductors in the interconnect structure of an IC die. By way of further example, vias may also be formed that extend from the backside of an IC die to the active or front side, such vias often referred to as “through-silicon vias.” Through-silicon vias can, for example, be used to form backside interconnects for a pair of bonded wafers, the bonded wafers forming a wafer stack that is ultimately cut into a number of stacked die.
The aspect ratio of a via can be defined as a ratio of the via's depth (or length) to the via's diameter (or width). Through-silicon vias typically have relatively high aspect ratios due to the thickness of the semiconductor wafers used to fabricate integrated circuit devices. For example, through-silicon vias can have aspect ratios reaching 10:1, or greater. Semiconductor manufacturers have developed processes to create such high aspect ratio vias with substantially straight sidewalls; however, film deposition on the side walls of high aspect ratio vias can be difficult. For example, the ability to use sputtering and electroplating processes to deposit metal films and other materials may be limited for high aspect ratio vias. The formation of oxide films may also be difficult where the aspect ratio of a via is high.
The aspect ratio of a via can be decreased either by decreasing the via's depth and/or by increasing the via's diameter. Often the depth of a through-silicon via is a parameter that is “fixed” by the thickness of a semiconductor wafer, or by the extent to which the wafer's backside can be thinned. Thus, where the ability to decrease the via depth is limited, semiconductor manufacturers may turn to enlarging the via diameter in order to decrease the aspect ratio. However, as a through-silicon via extending from the wafer's backside approaches the front or active side—e.g., the region of the wafer where transistors and other active devices are formed—available “real estate” may be limited and interference with the integrated circuitry can be a concern.